Base platforms with combined ASIC and FPGA features and process of using the same

ABSTRACT

A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

FIELD OF THE INVENTION

This invention concerns integrated circuits (ICs), and particularly to configurable base platforms having both application-specific IC (ASIC) and field-programmable gate array (FPGA) features.

BACKGROUND OF THE INVENTION

Reference is made to application Ser. No. ______ (Atty. Dkt. 04-1485/L13.12-0286), filed on even date herewith by Gary S. Delp and George Wayne Nation for “Composable System-in-Package Integrated Circuits and Process of Composing the Same” and assigned to the same assignee as the present invention, the content of which is hereby incorporated by reference in its entirety. The Delp et al. application describes use of configurable base platforms in a system-in-package (SIP).

Conventional ICs had been fabricated by foundries according to designs from device manufacturers. The design process required extensive design and development procedures for placement of elements, signal routing and timing to achieve correct operation of the IC.

More recently, configurable base platforms have become widely used as efficient and economic alternatives to traditional ICs. Configurable base platforms are characterized by a transistor fabric and at least some standard modules that are configurable by the addition of metallization layers or firmware into a functional device. Usually, the configurable base platform included a transistor fabric which is configured to implement a device manufacturer's (customer's) unique circuits, called “customer intellectual property” or simply “customer IP.” In the aforementioned Delp et al. application, we describe use of a configurable base platform that does not have many of the standard modules, such as large memory, input/output (I/O) modules, processors, etc. Instead, standard die provide these standard functions, and the die and platform are packaged together as a SIP.

The present invention is directed to a base platform that includes both ASIC and FPGA features, and to a process of configuring the platform to a usable device. The hybrid platform thus provides the advantage of the speed of ASICs and the ease of expansion and modification of FPGAs. While combined ASIC and FPGA packages are known, there is a need for a configurable base platform with ASIC and FPGA features and a process that allows customer to configure both the ASIC and FPGA features of such base platforms.

SUMMARY OF THE INVENTION

In one embodiment, the invention provides a process of configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified hardware design language (HDL) description of a circuit to be embodied in the platform is prepared, and a module map of the HDL description is annotated to identify memory programmable functions. Memory programmable logic refers to a type of configurable logic where logic functions and the interconnections of functions are programmed via configuration bits (i.e., memory). Memory programmable logic is one prevalent form of FPGA logic. The memory programmable functions are grouped for assignment to FPGA modules. A base platform is selected containing ASIC and FPGA modules adequate to execute the plurality of functions. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules to define signal routing and boundary timing closure for the configured platform.

The platform is configured by adding a metallization layer to configure the ASIC modules and creating a firmware memory image to configure the FPGA modules.

In another embodiment, a hybrid platform containing ASIC and FPGA features is provided.

In another embodiment, the platform is over-provided with FPGA features, and a controller is operable to selectively substitute functions performed in or controlled by the FPGA modules for logic functions in the ASIC modules, thereby permitting post-fabrication modification of the functions of the platform without re-working the platform design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a process of configuring the base platform for both ASIC and FPGA features.

FIG. 2 is a flowchart of a process of testing and modifying a configured base platform.

FIGS. 3 and 4 are diagrams illustrating an overprovisioning feature to permit substitution of an updated logic function in FPGA for an initial logic function in ASIC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In one form, base platforms according to the present invention include hardmacs composed of embedded transistors and other electronic circuit elements diffused into the semiconductor layers of the base platform and configured as memories, transceivers, arithmetic processors, analog-to-digital (A/D) and digital-to-analog (D/A) converters, I/O, etc. Arrays of pre-diffused transistors, sometimes called the “transistor fabric,” are arranged in a grid pattern to support user-defined memory and logic. The base platforms also include configurable logic blocks (CLBs) that are programmable by firmware loaded into configuration memories on the platform.

In another form, the hardmacs are not included on the base platform. Instead, the base platform is composed of the transistor fabric to support user-defined memory and logic, CLBs and memory to support the platform. Separate die are configured as memories, transceivers, processors, converters, I/O, firmware memory, etc. to support the configured platform as described in the aforementioned Delp et al. application.

In use, the device manufacturer employs tools known and practiced in the industry to design the metallization layer(s) to configure the transistor fabric into logic and memory functions and to design firmware for a configuration memory to configure the CLBs into FPGA functions. In a version of the base platform that includes hardmacs, the metallization layer(s) also interconnect the circuit elements to configure the hardmacs into operable relation.

A process of configuring the base platform for both ASIC and FPGA features is presented in FIG. 1. The process is segmented into four sections. Section 100 defines the steps taken by the user (device designer) to create a Hardware Description Language (HDL) description of an IC to be fabricated from a base platform according to the present invention. Section 102 describes a process of partitioning the hardware components into the die and base platforms where the base platforms that do not include hardmac functions (i.e., the platform will be part of an SIP that includes separate die containing the hardmacs). At section 104 the physical design of the base platform is created, and at section 106 the configured platform is fabricated.

At step 110 a functional specification is created for the platform or SIP to be fabricated. At step 112, the functions are separated into hardware and software functions. Firmware for programming the CLBs is abstracted out of the specification at this time. Software is separately developed at step 114. At step 116, functional blocks of hardware are defined in a hardware description language, such as a Verilog Register Transfer Level (RTL) description. The RTL description is verified at step 118, and the functional blocks are modified until a satisfactory design is achieved.

Upon completion of a verified RTL description of the hardware design, the process continues to section 102 to partition of the hardware components between the base platform and die for an SIP, or to section 104 for a complete platform. It is not always necessary to complete verification of the RTL design before entering section 102. However, subsequent changes to the HDL description due to errors found in verification step 118 will cause interruptions to the design steps of 102, 104, and 106. Even with these possible interruptions, proceeding with design implementation before completing verification is a common practice.

In the case of an SIP, optional step 120 sets forth the procedure of separating the hardware functions into hard and soft functions for the platforms and die of an SIP as described in the aforementioned Delp et al. application. A hard function is one that can be executed by a standard circuit die from the foundry's standard die library, while a soft function is one requiring user-defined logic or memory in a platform. Each hard function is assigned to a standard die, called a “sidecar,” selected from the foundry's die library and capable of executing the function. Firmware is fixed (loaded) into at least one of the memory die for the FPGA functions in a manner well known in the art.

In section 104, the platform design from section 100 (for a single IC) or section 102 (for an SIP), is supplied to step 130. At step 130, a module map of the hardware for the platform is created and the RTL is annotated with identification of the target logic type, such as ASIC or FPGA. The memory programmable modules are grouped at step 132 for assignment to one or more CLBs in the base platform. Preferably, the die and platform are selected with excess function (excess memory, logic, etc.) to over-provide the platform and die with elements for future expansion. More particularly, the size of the memory programmable modules may be enlarged for additional signal capabilities so that the memory-programmable functions can be expanded for additional signals in future versions of the circuit. Anticipating and identifying these signals is done is step 132.

At step 134, interfaces for the FPGA modules are defined. More particularly, the power and signal paths for the FPGA modules are defined, and if the platform is one for a SIP, interfaces between the die and platform are defined as described in the aforementioned Delp et al. application. At step 136, a base platform is selected with adequate CLB, optional hardmacs and transistor fabric to support the FPGA and ASIC functions for the IC or SIP. In some embodiments more fully described in conjunction with FIGS. 3 and 4, the selected base platform is overprovided with CLB and interface control to permit future substitution of logic initially formed in the transistor fabric with programmed logic in the FPGA fabric.

If the platform does not include hardmacs, as for a SIP, at step 138 the platform is recast with interconnect modules and logic substituted for sidecar die as described in the aforementioned Delp et al. application. Otherwise the process proceeds directly to step 140. At step 140 the non-memory programmable (metal-configured) modules are synthesized and placement and time closure is performed for the boundary nets. At step 142, the memory programmable (CLB) modules are synthesized, and placement and timing closure is completed for the entire platform.

The process ends with step 150 and fabrication of the configured platform with the firmware loaded into memory. The memory is a configuration memory that is either on platform (for an IC), in a separate die (in the case of a SIP), or in an off-platform configuration controller for either case. In either case, the memory containing the firmware is a configuration memory that configures the CLBs for the FPGA.

The platform is then assembled into a flipchip or wirebond for a SIP, as described in the aforementioned Delp et al. application, or packaged for assembly into an electronic device by the device manufacturer.

FIGS. 3 and 4 are diagrams illustrating an over-provisioning of programmable logic (CLBs) and FPGA signal interfaces to bypass initial logic formed in the transistor logic. The feature is particularly useful for upgraded and improved circuits and permits future addition and substitution of logic functions without re-fabricating the platform.

FIG. 2 illustrates a process of testing and modifying a platform configuration according to an embodiment of the present invention. Ordinarily, the process of FIG. 2 is used in conjunction with the process of FIG. 1. The process begins with a configured platform design at step 160. The platform is tested at step 162 to determine if the memory programmable logic (e.g., FPGA functions) satisfies the specifications for the IC. More particularly, tests are performed on the platform to identify conformance to the specifications input at step 110 (FIG. 1). If all of the memory programmable logic conforms to the product specifications, as identified at step 164, then the process ends at step 172 identifying that the configured platform is available for use.

If, at step 164 some memory programmable logic is not in conformance to the specifications, then at step 166 the RTL that was annotated at step 130 (FIG. 1) for the memory programmable logic modules that are not in conformance with the specifications is identified for modification. More particularly, the RTL description to be modified is identified by the annotations corresponding to the modules requiring modification. Modification of the RTL attempts to bring the module into specification requirements in a manner well known in the art.

At step 168 the modules that were modified at step 166 are synthesized, and placement and timing closure is completed for the entire platform, as at step 142 in FIG. 1. It will be appreciated that the re-synthesis is applied only to the modules modified at step 166, but the placement and timing closure is performed for the entire platform. The configured platform design is tested at step 170, such as by repeating step 162 on the entire design. Steps 164-170 are iteratively repeated until a satisfactory design id identified at step 164, whereupon the process ends at step 172.

FIG. 3 illustrates a portion of a base platform having a configured metal programmed fabric (ASIC) 200 and electrically programmable fabric (FPGA) 202 containing dormant logic blocks, such as CLBs. The CLBs are dormant in the sense that they are not yet programmed to execute any given logic function. Thus, in FIG. 3, the metal programmable fabric, such as the transistor fabric, has been configured into initial logic and memory functions by one or more metal layers. Thus, a metal programmed logic block 204 has been hardwired in the transistor fabric by the interconnection by the metal layer(s).

Multiplexer 208 is coupled to logic 204 to output the results of execution of the logic function of logic 204 on input data. Multiplexer has a second input 212 and an enable input 210, coupled to the FPGA module through buffers 214 on both modules. More particularly, with logic 204 operatively executing logic functions on input data, enable 210 and input 212 are fixed to a low logic level. Input data are applied to logic 204 and to a termination block 216 in FPGA module 202, such as through buffers 214.

Initially, the circuit operates with logic 204 hardwired in the transistor fabric by the metal interconnect layer(s). Input data are input to logic 204 to perform logic functions on the input data and provide a result to multiplexer 208. A fixed logically low enable input 210 to multiplexer 208 operates the multiplexer to output the result from logic 204.

Should it become necessary or desirable to update or change the logic function performed on the input data by logic 204, CLBs in the electronically programmable fabric 202 are programmed by firmware in a configuration memory to configure a new or replacement logic function 206 in the electronically programmable fabric Input data are input to logic 206 instead of termination block 216, and the results of the logic function are output to input 212 of multiplexer 208. The enable input 210 of multiplexer 208 is fixed to a high logical level so that multiplexer provides an output of the results of logic 206 in place of logic 204. Thus, using firmware in a configuration memory, logic 206 can be configured to perform a new logic function which can be substituted into the circuit in place of logic 204, without altering the physical properties of the platform. Thus, a device manufacturer might define new or changed logic functions for a next-generation circuit, and, with a base platform according to the present invention, program the new or changed logic function into logic 206. This feature is particularly useful for upgrading the device manufacturer's circuit without physically altering the platform.

While the over-provisioning feature is described in conjunction with substituting an FPGA function for an ASIC function, the concept may also be applied to couple off-chip functions, such as logic, memory, processing, I/O, etc. through the FPGA module. More particularly, input data may be supplied to and processed by an off-chip device. The result is then returned to logic 206 for gating through multiplexer 208.

The over-provisioning of FPGA signal interfaces with data and control signals is sufficient to control the bypass of ASIC control logic and functional replacement by a post-design update of the control logic in FPGA. Initially, the FPGA modules are dormant, except for logic for isolating the overprovisioned signal paths and supporting circuitry e.g., multiplexer 208. Datapath signals to and from the ASIC modules permit the ASIC modules to execute functions for the circuit in a first or initial configuration of the platform. Later addition or modification of firmware in the configuration memory, which is preferably in an off-chip controller, updates the dormant FPGA modules to process data to perform some new or updated function in place of the function performed by the bypassed ASIC module, without physical modification of the platform.

The present invention thus provides a hybrid base platform containing both ASIC and FPGA features and a process of configuring the platform into a functional IC as an independent IC or for use in a SIP.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. 

1. A process of designing a base integrated circuit platform having ASIC and FPGA modules to perform memory programmable functions and non-memory programmable functions, comprising steps of: a) preparing a verified hardware description of a circuit to be embodied in the platform; b) grouping the memory programmable functions for assignment to FPGA modules; c) selecting a base platform design containing ASIC and FPGA modules adequate to execute the plurality of functions; d) synthesizing the non-memory programmable functions to ASIC modules and the memory programmable functions to FPGA modules; and e) defining placement, signal routing and boundary timing closure.
 2. The process of claim 1, further including the step of configuring the platform by adding at least one metallization layer to the platform to configure the ASIC modules, and creating a configuration memory image to configure the FPGA modules.
 3. The process of claim 2, wherein at least some functions are standard functions executable in separate die for packaging with the configured base platform, the process further including steps of: before step b), separating the plurality of functions into standard functions and user-defined functions, and assigning the standard functions to die and the user-defined functions to the platform, wherein step b) is performed on the platform functions.
 4. The process of claim 3, wherein each die function is representable by respective die logic and the process further includes, before step d), a step of defining a configuration of the base platforms based on the die logic.
 5. The process of claim 1, further including, before step b), a step of: identifying the memory programmable functions.
 6. The process of claim 5, wherein step b) comprises steps of annotating a module map of the hardware description to identify the memory programmable functions, and grouping the memory programmable functions for assignment to FPGA modules based on the annotated module map.
 7. The process of claim 1, wherein at least some functions are embodied in separate die for packaging with the configured base platform, the process further including steps of: before step b), separating the plurality of functions into standard functions and user-defined functions, and assigning the standard functions to die and the user-defined functions to the platform, wherein step b) is performed on the platform functions.
 8. The process of claim 7, wherein step b) comprises steps of annotating a module map of the hardware description to identify memory programmable functions, and grouping the memory programmable functions for assignment to FPGA modules based on the annotated module map.
 9. The process of claim 7, wherein each die function is representable by respective die logic and the process further includes, before step d), a step of defining a configuration of the base platforms based on the die logic.
 10. The process of claim 1, further including replacing logic functions in the transistor logic by steps of: programming at least one FPGA module to substitute logic functions to replace non-memory programmable functions assigned to at least one ASIC module, and controlling outputs from the at least one FPGA and the at least one ASIC module to output results from the at least one FPGA module in place of results from the at least one ASIC module.
 11. The process of claim 1, further including steps of: testing the synthesized FPGA modules to identify conformance to a specification for which the hardware description was prepared, modifying the memory programmable functions for FPGA modules that are not in conformance to the specification, and re-synthsizing the modified memory programmable functions to FPGA modules.
 12. A base platform design for a configurable integrated circuit platform defining a memory for storing data, a diffused transistor fabric containing a plurality of transistors configurable to logic and memory, and configurable logic blocks, the transistor fabric being configurable by the addition of at least one metallization layer to the platform to selectively connect transistors of the transistor fabric into logic and/or memory and the logic blocks being configurable by firmware to execute functions on signals.
 13. The base platform design according to claim 12, wherein the design further defines hardmacs, including memory, and at least one memory containing the firmware.
 14. The base platform design according to claim 12, characterized by the absence of memory for the firmware, wherein the firmware is arranged to be resident in an off-platform configuration memory.
 15. The base platform design according to claim 12, further including second configurable logic blocks, the metallization layer selectively connecting the second logic blocks to the transistor fabric to receive input signals to logic formed in the transistor fabric, the second logic blocks being configurable by firmware to execute functions on the input signals, and a controller for selectively outputting results from the logic formed in the transistor fabric or the second logic blocks.
 16. The base platform design according to claim 15, wherein the controller is a multiplexer coupled to the logic in the transistor fabric and the second configurable logic blocks, and an enable input selectively controlling the multiplexer to output the results from either the logic formed in the transistor fabric or the second logic blocks.
 17. A process of upgrading an integrated circuit comprising first logic hardwired in the integrated circuit to perform a first function on data, programmable logic blocks connected to receive the data, and a controller for selectively outputting results from the first logic and the programmable logic blocks, the process comprising steps of: programming the programmable logic blocks to perform a second function; and operating the controller to output results from the programmable logic blocks.
 18. The process of claim 17, further comprising a step of: operating the controller to block output of results from the first logic.
 19. The process of claim 17, wherein the second functions are logic functions performed on data.
 20. The process of claim 17, wherein the second functions operate off-chip devices to perform functions on data. 